The present invention relates generally to a method for manufacturing a phase change memory device, and more particularly to a method for manufacturing a phase change memory device that can form stable top electrode contacts.
Memory devices are largely divided into a volatile RAM (random access memory) sub-category that loses inputted information when power is interrupted and into a non-volatile ROM (read-only memory) sub-category that can continuously maintain the stored state of inputted information even when power is interrupted. As to well-known representative volatile RAMs, DRAMs (dynamic RAM) and SRAMs (static RAM) can be mentioned. As to well known representative non-volatile ROMs, a flash memory device such as the EEPROM (electrically erasable and programmable ROM) can be mentioned.
As is well known in the art, DRAMs are excellent memory devices but DRAMs require high charge storing capacity. Since the surface area of an electrode must be increased to achieve a high charge storing capacity, it is difficult to achieve a high level of integration in a DRAM. Further, difficulties are experienced in the flash memory devices because of the fact that flash memory devices often require that two gates are stacked upon each other. Therefore, flash memory devices require high operation voltages when compared to the power source voltage demands of volatile RAMs. Yet further, flash memory devices often times require separate booster circuits to supply the necessary voltage required for write and delete operations. Accordingly, it is difficult to achieve a high level of integration for flash memory devices.
Under these circumstances, it is not surprising that considerable amounts of research have been devoted towards actively developing alternate novel memory devices. Preferably these alternate novel memory devices should have simple configurations and should be capable of accomplishing a high level of integration while retaining many of the desirable characteristics of the non-volatile memory devices. As an example of an alternate novel memory device would be a phase change memory device which has recently been disclosed in the art.
In phase change memory devices, a phase change can occur in a phase change layer interposed between a bottom electrode and a top electrode from a crystalline state to an amorphous state when subjected to an electrical current flowing between the bottom electrode and the top electrode. Information stored in phase change memory cells is recognized by using a measurable difference in resistance between the crystalline state and the amorphous state. Because the specific resistance of the phase change layer in the amorphous state is higher than the specific resistance of the phase change layer in the crystalline state, then sensing the current flowing through the phase change layer can be used to “read” the contents in each cell. Accordingly, one can arbitrarily assign a logic value of ‘1’ or ‘0’ to correspond to the information stored in a phase change cell depending on the state of the phase.
In fabricating phase change memory devices, bit lines and their respective phase change cells have to be electrically connected with each other. After patterning the phase change layer and top electrodes to constitute the phase change cells, contacts (hereinafter referred to as “top electrode contacts”) are formed on the top electrodes. The bit lines are then formed to connect with the top electrode contacts.
However, although not illustrated and described in detail, in the conventional art, the overlap between the top electrode contacts and the top electrodes is not large. If the overlap even slightly deviates away from forming the top electrode contacts, the phase change layer zones, which underlies the top electrodes, are likely to be inadvertently etched, and as a result the top electrode contacts can directly contact the phase change layer. As a result of this slight misalignment and inadvertent etching of the phase change layer, the composition of a Chalcogenide compound forming the phase change layer can be partially chemically changed as well as etch loss of the phase change layer can occur. Accordingly, as a result of this scenario of slight misalignment and inadvertent etching of the phase change layer, the electrical performance characteristics of the phase change layer may become non-uniform.
To address some of the problems brought about by non-uniformization of the performance characteristics of the phase change layer resulting from composition changes and the etch losses, the top electrode contacts can be patterned to be much more larger so as to increase the overlap between the top electrode contacts and the top electrodes. However, in this case, as the size of the cells increases in the direction of word lines, the area of an entire semiconductor chip increases, whereby defeating the goal of achieving a high integration of the phase change memory device. Alternately, if the top electrode contacts are patterned on the top electrodes to have a decreased size, then the contact resistance between the top electrodes and the bit lines increases, and as a result the current flow from the bit lines to switching elements may change, or non-uniform contacts may be formed so that the bit lines are electrically open relative to the top electrodes.